Programmable logic devices (PLDs) are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.
Each programmable tile may include both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). In some FPGAs, the interconnect lines may include single, double, quad, and long lines, which refer to the relative lengths of the interconnect lines. The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Qualifying a programmable IC for purposes of determining a maximum clock rate at which the IC may be operated can be challenging, because programmable ICs are highly configurable. For example, the delay through a PIP is highly dependent on the context in which the PIP is used. Assuming a context that assumes a worst case delay for the context of a PIP may result in an underestimation of the maximum clock rate. Attempting to evaluate all possible combinations of PIP contexts for connections involving multiple PIPs may not be computationally feasible.